In a semiconductor memory device, e.g., an NAND flash memory, all or half of memory cells aligned in a row direction are connected through bit lines to latch circuits for writing and reading respectively, and a write or read operation is collectively performed with respect to all or half of the memory cells (e.g., memory cells of 2 to 16 kB) aligned in the row direction.
A write or read unit is called a page, and a block includes pages. Erasing with respect to memory cells is performed in unites of blocks. Electrons are extracted from the memory cells by an erase operation to negatively set a threshold voltage, and the electrons are introduced into the memory cells by a write operation, whereby the threshold voltage is positively set.
A multilevel memory has been recently developed, which sets one of threshold voltages (which are also referred to as threshold levels hereinafter) to one memory cell and stores data of bits. For example, when 4 threshold levels are provided, data of 2 bits can be stored in one cell; and when 8 threshold levels are provided, data of 3 bits can be stored in one cell. Further, when 16 threshold levels are provided, data of 4 bits can be stored in one cell.
On the other hand, miniaturization for processing a floating gate of an element has recently become rigorous, structure that stores electrons in MONOS cells has been also suggested, and density growth realized by three-dimensional arrangement has been devised in particular. However, a threshold value Vth of the MONOS cells decreases due to detrapping immediately after a write operation in some cases.
As a countermeasure, there is a method of again performing a verify operation after a first write sequence and again carrying out writing with respect to cells, which have not reached a target threshold value, in accordance with each threshold value. However, this method can solve the detrapping problem but increases a write time. That is, at the time of performing rewriting with respect to memory cells that have not reached a target threshold value, one write pulse could be supplied to each threshold level, but a write threshold value used for writing must be held in a data storage circuit in a sense amplifier until this write pulse is supplied, and a cache program for storing subsequent write data in the data storage circuit in advance cannot be executed in some cases.